Reference Book

R. Jacob Baker
"CMOS: Circuit Design, Layout, and Simulation"
(IEEE Press Series on Microelectronic Systems)
4th Edition, Wiley, 2019


Course Software

  • Electric: computer-aided design system for electrical circuits. It is primarily intended for integrated-circuit layout, but it also handles schematics and even textual hardware description languages
  • LTSpice: high performance SPICE simulation software, schematic capture and waveform viewer with enhancements and models for easing the simulation of analog circuits.

Course Goals

  • Design of Very Large Scale Integration (VLSI) systems.
  • Examination of layout and simulation of digital VLSI circuits using a comprehensive set of CAD tools in a laboratory setting.
  • Studies of layouts of CMOS combinational and sequential circuits using automatic layout generators.
  • Fundamental structures of the layout of registers, adders, decoders, ROM, PLA's, counters, RAM and ALU.
  • Application of statistics and probability to chip performance.
  • Use CAD tools to perform logic verification and timing simulation of the circuits designed.

Course Modules

  • Silicon structure
  • nMOS and pMOS
  • Basic logic gates structure
  • CMOS Fabrication
  • Layout
  • CMOS gate design
  • Pass transistors
  • CMOS latches and flip-flops
  • Standard cell layouts
  • Stick diagrams
  • Patterning
  • Laying Out the N-well
  • Resistance calculation
  • The RC delay through the N-well
  • The bonding pad
  • Design and layout using the metal layers
  • Layout using the active and poly layers
  • Connecting wires to poly and active
  • Layout of an NMOS and PMOS device
  • Standard cell frame
  • Design rules
  • ESD protection
  • DC Characteristics
  • Switching Characteristics
  • Layout of the inverter
  • DC Characteristics of the NAND and NOR gates
  • Layout of the NAND and NOR gates
  • Complex CMOS logic gates
  • The Schmitt Trigger
  • Multivibrators Circuits
  • Input Buffers
  • Charge Pumps
  • Floorplan, power plan, placements, clock tree synthesis, routing, static timing analysis
  • Verification and Analysis